Processes and devices for disabling ports in a network have been used in the past to traverse arbitrary graphs and convert the arbitrary graphs into acyclic graphs. However, all of these prior art processes and methods implement algorithms which are dependent on the number of ports the node has. In other words, the prior art processes and methods require that the number of ports each node has be fixed. For example, the prior art processes and methods would have a different algorithm for arbitrary graphs having 3-ported nodes as opposed to arbitrary graphs having 5-ported nodes.
Accordingly, the prior art methods and devices suffer from the disadvantage that a plurality of different methods and devices, each implementing an algorithm for nodes having a fixed number of ports, are required in order to solve arbitrary graphs having nodes with a different number of ports. In other words, it is necessary to implement a different algorithm for a 3-ported node as opposed to a 5-ported node. This increases the cost and complexity of designing chips for networks because a plurality of different devices and chip designs are required to satisfy nodes having a different number of ports.
A further disadvantage of the prior art is that if a process and device to implement an algorithm for an arbitrary graph having a specific number of ports per node was not available, it is necessary to "over design" for the arbitrary graph by implementing algorithms to solve the next largest number of ports on the node. For example, if only methods and devices for 3-ported nodes and 5-ported nodes have been designed, but a node has 4 ports, the algorithm for the 5-ported node would be implemented because no algorithm for a 4-ported node has been designed. While the algorithm for the 5-ported node arbitrary graph would operate for a 4-ported node arbitrary graph, there would be an unnecessary cost in having elements to implement the algorithm for the 5-ported node when a device implementing a 4-ported node algorithm would suffice. In addition, more space would be required on a chip to implement an algorithm for a 5-ported node arbitrary graph rather than an algorithm for a 4-ported node arbitrary graph, thereby decreasing the available space or real estate on the chip for other uses.